STR720 datasheet(63/401 Pages) STMICROELECTRONICS

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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Interrupt Pending Register 0 (IPR0)

Address Offset: 40h

Reset value: 0000 0000h

Bit 31= IPR[31]: Channel 31 Interrupt Pending bit

Bit 30 = IPR[30]: Channel 30 Interrupt Pending bit

...

Bit 1 = IPR[1]: Channel 1 Interrupt Pending bit

Bit 0 = IPR[0]: Channel 0 Interrupt Pending bit

The IPR0 is a 32 bit register: it provides a pending bit for each of the 32 EIC interrupt input

channels.

This is where actually the information about the channel interrupt status is kept: if the

corresponding bit in the enable register IER0 has been set, the IPR0 bit set high (active)

means that the related channel has asserted an interrupt request that has not been serviced

yet.

The bits are Read/Clear, i.e. writing a ‘0’ has no effect, whereas writing a ‘1’ clears the bit

(forces it to ‘0’).

1: Interrupt pending

0: No interrupt pending

Note

Before exiting the ISR (Interrupt Service Routine), the software must be sure to have

cleared the EIC IPR0 bit related to the executed routine: this bit clear will be read by

the EIC logic as End of Interrupt (EOI) sequence, and will allow the interrupt stack

pop and new interrupts processing .

IPR[31:16]

765432

IPR[15:0]

STR720 数据表(PDF) 63 Page - STMicroelectronics