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STR720 数据表(PDF) 24 Page - STMicroelectronics

部件名 STR720
功能描述  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STR720 数据表(HTML) 24 Page - STMicroelectronics

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STR720 - PIN DATA
24/401
MECHANICAL DATA” on page 373. In the following drawing and table the device pin mapping
is reported
Figure 3. STR720 PQFP208 pin configuration (top view)
VDD3
VSS
EMI/IDE D14
EMI/IDE D7
EMI/IDE D15
#Byte (P7.40)
EMI A16
VDD18
GND
VDD3
GND
P4.4
P4.3
AGCDATA
P4.1
P4.0 Eready
GPSCLK
ACQCLK
PECLREF
MAG
SIGN
VDD3P
VSSP
VDDDAC
DAC Filter
DAC-
DAC+
DAC-Iref
GNDDAC
VDD3
GND
AVDD
A/D0
A/D1
A/D2
A/D3
AGND
JTDO
JTCK
JTMS
JTDI
#JTRST
BLS2
D23
D22
VDD3
GND
D21
D20
D19
D18
D17
D3
D2
D1
D0
D15
D14
D13
D12
VDD3
GND
D11
D10
D9
D8
BLS1
GNDPLL
VDDPLL
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
VDD3
GND
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
VDD18
GND18
GND
VDD3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6 (EXT_BOOT)
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
Tuareg pinout V0.4
VDD3
VSS
EMI/IDE D14
EMI/IDE D7
EMI/IDE D15
#Byte (P7.40)
EMI A16
VDD18
GND
VDD3
GND
P4.4
P4.3
AGCDATA
P4.1
P4.0 Eready
CLK
Reserved
VREF
Reserved
Reserved
VDD3P
VSSP
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VDD3
GND
AVDD
A/D0
A/D1
A/D2
A/D3
AGND
#JTRST
JTCK
JTMS
JTDI
JTDO
BLS2
D23
D22
VDD3
GND
D21
D20
D19
D18
D17
D3
D2
D1
D0
D15
D14
D13
D12
VDD3
GND
D11
D10
D9
D8
BLS1
GNDPLL
VDDPLL
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
VDD3
GND
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
VDD18
GND18
GND
VDD3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6 (EXT_BOOT)
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
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