STR720 datasheet(88/401 Pages) STMICROELECTRONICS

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STR720 - DMA CONTROLLER (DMAC)

88/401

Control register 2 (DMACtrl2)

Address Offset: 94h

Reset value: 0000h

DMACtrl2 register is used to configure stream 2 operations.

Bit 0 = Enable: DMA enable

0: DMA disable

1: DMA enable

Bit 1 = SoInc: Increment Current Source Register

This bit is used to enable the Current Source Register after each source to DMA data transfer.

0: Current Source Register unchanged

1: Current Source Register incremented

Bit 2 = DeInc: Increment Current Destination Register

This bit is used to enable the Current Destination Register after each DMA to destination data

transfer.

0: Current Destination Register unchanged

1: Current Destination Register incremented

Bit 4:3 = SoSize: Source to DMA data width

These bits are used to select the data width for source to DMA data transfer.

00: 1 byte

01: 1 half-word

10: 1 word

11: reserved

Bit 6:5 = SoBurst: DMA peripheral burst size

These bits are used to define the number of words in the peripheral burst. When the

peripheral is the source (Dir = 0), SoSize words are read in to the FIFO before writing FIFO

contents to destination. When the peripheral is the destination (Dir = 1), the DMA interface will

automatically read the correct number of source words to compile an SoBurst of the DeSize

data.

00: Single

01: 4 incrementing

10: 8 incrementing

11: 16 incrementing

765432

reserved

Dir

reserved

Circular

DeSize

SoBurst

SoSize

DeInc

SoInc

Enable

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