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STR720 数据表(PDF) 56 Page - STMicroelectronics

部件名 STR720
功能描述  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STR720 数据表(HTML) 56 Page - STMicroelectronics

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)
56/401
7.4 Register Description
Reading from the “Reserved” field in any register will return ‘0’ as result. Attempt to write in the
same field has no effect.
Interrupt Control Register (ICR)
Address Offset: 00h
Reset value: 0000 0000h
Bit 31:2 = Reserved.
Bit 1= FIQ_EN: Global FIQ output ENable bit
This bit enables FIQ output request to the CPU.
1: Enhanced Interrupt Controller FIQ output request to CPU is enabled
0: Enhanced Interrupt Controller FIQ output request to CPU is disabled, even if the EIC logic
has detected valid and enabled fast interrupt requests at its inputs
Bit 0 = IRQ_EN: Global IRQ output ENable bit
This bit enables IRQ output request to the CPU.
1: Enhanced Interrupt Controller IRQ output request to CPU is enabled
0: Enhanced Interrupt Controller IRQ output request to CPU is disabled, even if the EIC logic
has detected valid and enabled interrupt requests at its inputs
The ICR register is an enable register at the EIC IRQ/FIQ outputs level: it has no influence on
the EIC internal logic behaviour.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
-
15
14
13
12
11
10
9
8
765432
1
0
reserved
FIQ_EN IRQ_EN
-rw
rw
1



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