STR720 datasheet(96/401 Pages) STMICROELECTRONICS

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STR720 - DMA CONTROLLER (DMAC)

96/401

Interrupt Clear Register (DMAClr)

Address Offset: F4h

Reset value: 0000h

The DMA Clear Register is used to clear the status flags. This is a write-only register and it will

return 0000h every time it is read.

Bits 1:0 = Reserved. They must always be written to 0.

Bit 2 = SIC2: Stream 2 Interrupt Clear

This bit allows clearing the pending interrupt flag corresponding to stream 2 transfer end

event.

1: Clear INT2 flag in DMAStatus register

0: No effect

Bit 3 = SIC3: Stream 3 Interrupt Clear

This bit allows clearing the pending interrupt flag corresponding to stream 3 transfer end

event.

1: Clear INT3 flag in DMAStatus register

0: No effect

Bits 5:4 = Reserved. They must always be written to 0.

Bit 6 = SEC2: Stream 2 Error Clear

This bit allows clearing the pending interrupt flag corresponding to stream 2 transfer error

event.

1: Clear ERR2 flag in DMAStatus register

0: No effect

Bit 7 = SEC3: Stream 3 Error Clear

This bit allows clearing the pending interrupt flag corresponding to stream 3 transfer error

event.

1: Clear ERR3 flag in DMAStatus register

0: No effect

Bit 15:8 = Reserved. They must be always written to ‘0’

765432

reserved

SEC3

SEC2

res.

SIC3

SIC2

rese.

res.

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