STR720 datasheet(30/401 Pages) STMICROELECTRONICS

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STR720 - ARCHITECTURE OVERVIEW

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Interrupt Vector 6

•

UART2 interrupt request (see Interrupt Vector 5).

Interrupt Vector 7

•

DMA controller interrupt request.

Four different interrupt requests are OR-ed together to generate a single interrupt request:

•

Data stream 2 and 3 completed transfer interrupts

•

Data stream 2 to 3 transfer error interrupts

Interrupt Vector 8

•

Reserved.

Interrupt Vector 9

•

Reserved.

Interrupt Vector 10

•

USB interface high priority events interrupt request.

All isochronous and double-buffer endpoint correct transfer interrupt requests are OR-ed

together to generate a single interrupt request. The number of isochronous/

double-buffered endpoints is programmable by software, so the actual number of events

raising this interrupt line can vary from 0 to 7.

Interrupt Vector 11

•

USB interface low priority and generic events interrupt request.

All endpoint correct transfer interrupt requests, except isochronous and double-buffered

(see Interrupt Vector 10) are OR-ed together with the generic USB events to generate a

single interrupt request.

The USB events not related to endpoint activity are:

•

Data overrun/underrun

•

USB Error

•

USB Wake-up

•

USB Suspend

•

USB Reset

•

Start of frame

•

Missing start of frame

The number of isochronous/double-buffered endpoints is programmable by software, so

the actual number of events raising this interrupt line can vary from 7 to 15.

STR720 数据表(PDF) 30 Page - STMicroelectronics

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