STR720 datasheet(37/401 Pages) STMICROELECTRONICS

37 / 401 page

STR720 - ARCHITECTURE OVERVIEW

37/401

5.5 External Memory Interface

The External Memory Interface (EMI) controls the data flow from AHB bus to an external

memory components - both ROM, SRAM and PCMCIA Interface and it can access up to

8 Mbytes of memory space, possibly partitioned in 4 different memory banks.

The AHB interface manages 32 bit data that can be then packed/unpacked before being send

through a 16 bit data bus. The EMI will automatically unpack the data and reformat it to the

right part of the bus for write access. For read access, it will buffer the access to build the

complete 32-bit data to be send to the AHB.

The length of time required to properly transfer data to external memory components is

controllable by programming of internal registers dedicated to each external memory space.

In case the response time of the external device is not constant, a specific alternate function

is provided on P4.0 used as an external ready signal, whose transition flags the end of current

access. This external ready functionality can be enabled by programming the internal EMI

registers which also contain flag bits to inform the controller if a particular memory space is

accessible or not. These internal registers are accessed via an APB interface to the EMI

block.

The External Memory Interface shares a 46-bit port (port 7) with the IDE interface pins so that

the two interfaces cannot be used at the same time. The address bus starts from bit 0 (P7.16)

and ends on bit 21 (P7.37) always representing the 16-bit word location accessed by the EMI

block. The selection between EMI and IDE pins can be done by setting the corresponding bit

in SGCR1 register. Beside this limitation, also the number of accessible memory banks is

limited to 2: bank 0 will be always accessible while bank 1 can be used only through a specific

I/O programming since its chip select line is shared with another GPIO pad (P4.4 = CS1).

Memory banks CS2 and CS3 are never accessible.

5.6 ATAPI IDE interface

ATA 4 Industry Standard EIDE controller. The controller allows interfacing to devices such as

Hard disk drives or CD ROM to the STR720 system being capable of transferring data either

under CPU control or using the DMA controller “memory-to-memory” transfer mode, thus

being able to spare CPU time even if PIO modes are configured. The IDE controller supports

the following features:

■

Primary-only channel, supporting up to two IDE devices.

■

Support for CD-ROM and tape peripherals.

■

Independently programmable timing for each device.

■

Programmable posted writes and read-prefetch.

■

Software selectable endianness for data read from CDROM / tape peripheral.

■

Support for I/O Channel Ready.

■

Support for PIO modes 0, 2, 3 and 4.

STR720 数据表(PDF) 37 Page - STMicroelectronics

STR720 数据表(HTML) 37 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载