STR720 datasheet(10/401 Pages) STMICROELECTRONICS

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STR720 - INTRODUCTION

10/401

1 INTRODUCTION

STR720 is an STMicroelectronics new generation super-integrated single-chip device.

It combines the high performance of ARM720T

™ CPU microprocessor (revision 3) with high

peripheral functionalities and enhanced I/O capabilities. It also provides on-chip high-speed

RAM, clock generation via PLL and several embedded custom digital logics. STR720 is

software compatible with the ARM processor family.

It is built using 0.18

µm HCMOS8 process, with 1.8 V internal logic voltage and 3.3 V capable

I/O lines.

The ARM720T

™ is a member of the Advanced RISC Machines (ARM) family of general pur-

pose 32-bit microprocessors combining in a single chip an 8 KByte cache, an enlarged write

buffer, and a Memory Management Unit (MMU).

The ARM720T

™ belongs to the ARM7 family, making it software-compatible with all the ARM

processors.

The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles: its

instruction set and related decode mechanism are much simpler than those of

micro-programmed Complex Instruction Set Computers (CISC). This simplicity results in a

high instruction throughput and impressive real-time interrupt response from a small and

cost-effective chip.

The on-chip mixed data and instruction cache, together with the write buffer, substantially rise

the average execution speed and reduce the average amount of memory bandwidth required

by the processor. This allows the external memory to support Direct Memory Access (DMA)

channels with minimal performance loss.

The MMU supports a conventional two-level, page-table structure and a number of extensions

that make it ideal for embedded control, UNIX, and object-oriented systems. The allocation of

virtual addresses with different task IDs improve performance in task switching operations

with the cache enabled. These relocated virtual addresses are monitored by the

Embedded-ICE block.

The memory interface is designed to allow the performance potential to be realized without

incurring high costs in the memory system. Speed-critical control signals are pipelined to

allow system control functions to be implemented in standard low-power logic, and these

control signals facilitate the exploitation of the fast local access modes offered by

industry-standard DRAMs.

For more information on the ARM720T core please refer to the ARM720T Rev 3 Technical

Reference Manual.

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