STR720 datasheet(51/401 Pages) STMICROELECTRONICS

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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7 ENHANCED INTERRUPT CONTROLLER (EIC)

7.1 Introduction

The ARM720T CPU provides two levels of interrupt, FIQ (Fast Interrupt Request) for fast, low

latency interrupt handling and IRQ (Interrupt Request) for more general interrupts.

Hardware handling of multiple interrupt channels, interrupt priority and automatic vectorization

require therefore a separate Enhanced Interrupt Controller (EIC).

7.2 Main Features

■

32 maskable interrupt channels, mapped on ARM’s interrupt request pin IRQ

■

16 programmable priority levels for each interrupt channels mapped on IRQ

■

hardware support for interrupt nesting (16 levels)

■

3 maskable interrupt channels, mapped on ARM’s interrupt request pin FIQ, with neither

priority nor vectorization

Figure 7. EIC block diagram

IRQ0

IRQ1

IRQ31

IER0-IER1

FIQ0

FIQ1

FIR

FIQ

control logic

IRQ

control logic

FIQ request

IRQ request

STACK CTL (PUSH/POP)

PRIORITY

STACK

(16 ENTRY)

CIPR

FIQ to

ARM720T

Highest Priority Interrupt

SIR

(32 ENTRY)

IRQx

VECTOR

IE0

IE1

IE31

IP0

IP1

IP31

IPR0-IPR1

FIE[0]

FIE[1]

FIR

FIP[0]

FIP[1]

IRQ_EN

ICR

FIQ_EN

SIRn(31:16)

IVR(31:16)

Interrupt from line IRQx

IVR

IRQ to

ARM720T

FIE[2]

FIP[2]

FIQ2

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