STR720 datasheet(57/401 Pages) STMICROELECTRONICS

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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Current Interrupt Channel Register (CICR)

Address Offset: 04h

Reset value: 0000 0000h

The CIC Register reports the number of the interrupt channel currently serviced. There are 32

possible channel IDs (0 to 31), so the significant register bits are only five (4 down to 0).

After reset, the CIC value is set to ‘0’ and is updated by the EIC logic only after the processor

has started servicing a valid IRQ interrupt request.

To make this happen, some EIC registers must be set as in the following:

•

ICR IRQ_EN =1

•

IER not all 0 (at least one interrupt channel must be enabled)

•

among the interrupt channels enabled by the IER registers, at least one must have the

SIPL field, of the related SIR register, not set to 0, because the EIC generates a processor

interrupt request (asserting the nIRQ line) ONLY IF it detects an enabled interrupt request

whose priority value is bigger than the CIPR (Current Interrupt Priority Register)

value.

When the nIRQ line is set, the processor will read the EIC IVR (Interrupt Vector Register), and

this read operation will advise the EIC logic that the ISR (Interrupt Service Routine) has been

initiated and the CICR register can be properly updated.

The CICR value can’t be modified by the CPU (read only register).

Bit 31:5 = Reserved.

Bit 4:0 = CIC[4:0]: Current Interrupt Channel.

Number of the interrupt whose service routine is currently in execution phase.

reserved

765432

reserved

CIC[4:0]

-r

STR720 数据表(PDF) 57 Page - STMicroelectronics