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STR720 数据表(PDF) 32 Page - STMicroelectronics |
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STR720 数据表(HTML) 32 Page - STMicroelectronics |
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32 / 401 page  STR720 - ARCHITECTURE OVERVIEW 32/401 5.1.2 FIQ Interrupt Vector Table Three maskable interrupt sources are mapped on FIQ vectors: • FIQ0: External interrupt channel 0 • FIQ1: Extended Function Timer 2 output compare B interrupt request • FIQ2: AHB Error detection interrupt request Table 13. IRQ Interrupt Vector Summary Vector Peripheral Peripheral Interrupt Flags IRQ0 IRQ03IT: External Interrupts EINT0-EINT3 4 IRQ1 IRQ4IT: External Interrupt EINT4 1 IRQ2 WIUIT: WIU wake-up event interrupt 11 IRQ3 EFT1IT: EFT1 global interrupt 5 IRQ4 EFT2IT: EFT2 global interrupt 3 IRQ5 UART1IT: UART 1 global interrupt 9 IRQ6 UART2IT: UART 2 global interrupt 9 IRQ7 DMAIT: DMA event global interrupt 4 IRQ8 Reserved. IRQ9 Reserved. IRQ10 USBHPIT: USB high priority event interrupt 0 - 7 IRQ11 USBLPIT: USB low priority event interrupt 7 - 15 IRQ12 CANIT: CAN module general interrupt 32 IRQ13 BSPI1IT: BSPI 1 global interrupt 5 IRQ14 BSPI2IT: BSPI 2 global interrupt 5 IRQ15 IDEPIRQ: IDE Primary channel interrupt 1 IRQ16 RTCPERIT: RTC Periodic interrupt 1 IRQ17 Reserved. IRQ18 Reserved. IRQ19 Reserved. IRQ20 Reserved. IRQ21 Reserved. IRQ22 Reserved. IRQ23 ADCIT: ADC sample ready interrupt 1 IRQ24 Reserved. IRQ25 Reserved. IRQ26 Reserved. IRQ27 Reserved. IRQ28 Reserved. IRQ29 EFT2OCA: EFT2 Output Compare A Interrupt 1 IRQ30 EFT2OCB: EFT2 Output Compare B Interrupt 1 IRQ31 WDGIT: WDG timer interrupt 1 1 |
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