STR720 datasheet(61/401 Pages) STMICROELECTRONICS

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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Fast Interrupt Register (FIR)

Address Offset: 1Ch

Reset value: 0000 0000h

In order for the controller to react to the 3 fast-interrupt (FIQ) channels the enable bits from 2

down to 0 must be set to 1. The field 5 down to 3 keeps the information on the interrupt

request of the specific channel.

Bit 31:6 = Reserved.

Bit 5 = FIP[2]: Channel 2 Fast Interrupt Pending Bit

Bit 4 = FIP[1]: Channel 1 Fast Interrupt Pending Bit

Bit 3 = FIP[0]: Channel 0 Fast Interrupt Pending Bit

These bits are set by hardware by a Fast interrupt request on the corresponding channel.

These bits are cleared only by software, i.e. writing a ‘0’ has no effect, whereas writing a ‘1’

clears the bit (forces it to ‘0’).

1: Fast Interrupt pending

0: No Fast interrupt pending

Bit 2 = FIE[2]: FIQ Channel 2 Interrupt Enable bit

Bit 1 = FIE[1]: FIQ Channel 1 Interrupt Enable bit

Bit 0 = FIE[0]: FIQ Channel 0 Interrupt Enable bit

In order to have the controller responding to a request on a specific channel, the

corresponding bit in the FIR register must be set to 1.

1: Fast Interrupt request issued on the specific channel is enabled

0: Fast Interrupt request issued on the specific channel is disabled

reserved

FIP[2:0]

FIE[2:0]

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