STR720 datasheet(43/401 Pages) STMICROELECTRONICS

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STR720 - ARCHITECTURE OVERVIEW

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Eight Endpoints are available; each may be software-configured to be Control/Interrupt/Bulk/

Isochronous. Double-buffering is supported for Bulk and Isochronous transfers.

CRC generation/checking, NRZI encoding/decoding, bit-stuffing and packet filtering are

handled by hardware; interrupt is generated at the end of each packet correctly sent/received,

or on transmission errors. Packets are stored in an internal buffer memory implemented as a

single port 512 x 16 bit RAM.

USB suspend/resume are fully supported, allowing to stop the system clocks while keeping

the wake-up capability and be compliant with USB current consumption specifications for bus

powered devices.

5.15 WatchDoG timer (WDG)

The watchdog timer represents one of the fail-safe mechanisms which have been

implemented to prevent the controller from malfunctioning. It is able to generate a system

reset upon expiration of a programmed period of time.

The watchdog timer can be enabled by software. When RSTIN pin is released, the Watchdog

Timer is not enabled, and it must be activated by software: once enabled, it can no longer be

disabled by software. A prescaler allows to widely program the WDG overflow period whose

length depends upon the selected WDG clock using EE bit of WDTCR register: if APB clock is

selected, writing EE to ‘0’, the period can range between 66 ns and 0.5 s (with APB clock at

30 MHz), otherwise if low frequency clock (4 kHz derived from the 32 kHz RTC clock) is

selected, writing EE to ‘1’, the period can be extended between 500

µs to about 4200 s

independently from system clock frequency.

To prevent a system Reset the application code shall write, with a particular sequence, the

Watchdog Timer Control Register at regular intervals. At the end of a successful write

operation the Watchdog Timer restarts to count from the preset value. In order to prevent a

system reset, the user has to write the sequence A55A, 5AA5 in the WDTKR register of WDG

peripheral.

The Watch DoG timer can also be used as a free-running timer, providing an interruption

request when counting down counter reaches 0.

5.16 Extended Function Timer (EFT)

The STR720 system includes 2 Extended Function Timers (EFT). Each EFT consists of a

16-bit counter driven by a programmable prescaler.

They may be used for a variety of purposes, including pulse length measurement of up to two

input signals (input capture) or generation of up to two output waveforms (output compare and

PWM). Pulse lengths and waveform periods can be modulated from a very wide range using

the timer prescaler.

Not all their alternate function I/O features are available: only module EFT1 external clock

input function and one EFT2 output compare I/O line can be used. Regardless of the number

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