STR720 datasheet(65/401 Pages) STMICROELECTRONICS

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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Source Interrupt Registers - Channel n (SIRn)

Address Offset: 60h to DCh

Reset value: 0000 0000h

There are 32 different SIRn registers, as many as the input interrupt channels are.

Bit 31:16 = SIV[31:16]: Source Interrupt Vector for interrupt channel n (n = 0... 31).

This field contains the interrupt channel depending part of the interrupt vector, that will be

provided to the processor when the Interrupt Vector Register (Address 0x18h) is read.

Depending on what the processor expects (32 bit address or instruction, see IVR description),

the SIV will have to be loaded with the interrupt channel ISR address offset or with the lower

part (including the jump offset) of the first ISR instruction.

Bit 15:4: Reserved.

Bit 3:0 = SIPL[3:0]: Source Interrupt Priority Level for interrupt channel n (n = 0... 31).

These 4 bits allow to associate the interrupt channel to a priority value between 0 and 15. The

reset value is 0.

Note

To be processed by the EIC priority logic, an interrupt channel must have a priority

level higher than the current interrupt priority (CIP); the lowest value CIP can have is

0, so all the interrupt sources that have a priority level equal to 0 will never generate

an IRQ request, even if properly enabled.

SIV[31:16]

765432

reserved

SIPL[3:0]

-rw

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