STR720 datasheet(33/401 Pages) STMICROELECTRONICS

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STR720 - ARCHITECTURE OVERVIEW

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Having only one FIQ vector shared by the three interrupt sources, a polling on FIQ interrupt

pending bits contained inside EIC must be performed by the application code in order to

establish the exact source of interrupt, in case more than one FIQ source is enabled. Besides,

having no priority mechanism, in case of contemporaneous FIQ events, the software shall

manage the priority simply by polling the pending bits and managing the concurrence.

5.1.3

IRQ Interrupt Vectoring

The EIC (Enhanced Interrupt Controller) implements an interrupt structure pointing the

processor at the first instruction location of the channel-specific Interrupt (IRQ) Service

Routine.

IVR (Interrupt Vector Register) is the EIC’s 32-bit register at address 0xFFFF_FC18 acting as

pointer. It is composed by two main fields: the upper half word (16 bit) is directly

programmable, while the lower half word is the mirrored entry of a register table (named SIR)

indexed by the interrupt channel (see Chapter 7: ENHANCED INTERRUPT CONTROLLER

(EIC) on page 51).

The absolute address 0x0000_0018 is where the ARM720T CPU jumps as consequence of

an interrupt request on its IRQ pin.

The STR720 implementation is such that the ARM’s 0x0000_0018 location and the EIC’s IVR

location are considered as distinct addresses. The EIC IVR register can contain, for example,

the absolute address of the interrupt service routine or an index to a jump table; at location

0x0000_0018 the interrupt handling routine starts, using IVR as index or pointer to the actual

response routine. To implement this behaviour the absolute 0x0000_0018 location must

contain an instruction which allows to perform a jump to the location pointed to by the IVR

For instance, the absolute location 0x0000_0018 should contain the following instruction:

LDR PC, [PC, offset]

where “offset” is what to add to the PC to obtain the EIC IVR address. The instruction above

allows the CPU to load the Program Counter register with the address kept in EIC IVR and so

to jump to the location pointed to by the IVR register.

The user has to consider that when the absolute address 0x0000_0018 is being fetched, the

PC is equal to 0x0000_0020 (18h + 8h). So, the offset is equal to:

offset = IVR address – 0x0000_0020 = 0xFFFF_FC18 – 0x0000_0020 = 0xFFFF_FBF8

Table 14. FIQ Interrupt Vector Table

Vector

Interrupt Source

FIQ0

External Interrupt IRQ0

FIQ1

EFT2 Output Compare B Interrupt

FIQ2

AHB Error detection Interrupt

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