STR720 datasheet(39/401 Pages) STMICROELECTRONICS

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STR720 - ARCHITECTURE OVERVIEW

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independently stopped, freezing its clock input signal, by proper configuration registers

located in the A-APB bridge, in GCR registers and in a specific Clock Gating Control block.

If application software requires it, RCCU block can issue an interrupt, through the WIU block,

upon any change of PLL lock condition, so to take proper action when system clock frequency

is different from what is set in RCCU configuration.

For a detailed description of STR720 operating modes, see Chapter 25: POWER

REDUCTION MODES on page 364.

Note

The AHB and S-APB blocks are driven by the same clock signal (AHB_CLK) .

5.7.2

RESET management

The Reset Manager resets the MCU when one of the following events occurs:

– A Hardware reset, initiated by a low level on the Reset pin;

– A Software reset, forced setting a control bit inside the RCCU

– A Watchdog end of count condition (when enabled)

The event causing the last Reset is flagged in the CLKFLAG register: the corresponding bit is

set. A hardware initiated reset will leave all these bits reset.

The hardware reset overrides all other conditions and forces the system to the reset state.

During the Reset phase, the internal registers are set to their reset values, where these are

defined, and the I/O pins configuration is restored to the condition reported in Section 5.18:

General Purpose I/O Ports on page 44 and Section 5.19: Dedicated Pins on page 45.

Reset from pad is asynchronous: when it is driven low for a duration longer than the on-chip

RC filter width (between 50 ns and 500 ns), a Reset cycle is initiated (see Chapter 26:

SYSTEM RESET on page 370). The on-chip Watchdog Timer generates a reset condition if

the Watchdog mode is enabled and if the programmed period elapses without the specific

code written to the appropriate register (see Chapter 20: WATCHDOG TIMER (WDG) on

page 303).

When the Reset pin goes high again, the on-chip RC filter width plus 768 CLK plus 8

AHB_CLK cycles are counted before exiting the Reset state (plus possibly up to four

additional CLK period, depending on the delay between the rising edge of the Reset pin and

the first rising edge of CLK). As an example it corresponds to an interval between 48.25

µs

and 48.5

µs with a 16 MHz input clock.

At the end of the Reset phase, the Program Counter will be set to the location specified in the

Reset Vector located in the 0000 0000h location of memory.

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