STR720 datasheet(91/401 Pages) STMICROELECTRONICS

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STR720 - DMA CONTROLLER (DMAC)

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Bit 8:7 = DeSize: DMA to destination data width

These bits are used to select the data width for DMA to destination data transfer.

00: 1 byte

01: 1 half-word

10: 1 word

11: reserved

Bit 9 = Circular: Circular mode

This bit is used to enable DMA to operates in the circular buffer mode.

0: normal buffer mode

1: circular buffer mode

Bit 10 = Reserved. It must be always written to ‘0’.

Bit 11 = Mem2Mem: Selects memory to memory transfer

This configure stream 3 to operate a memory to memory transfer. When Mem2Mem is set, the

DMA will disregard the DMA request connected to stream 3, and transfer data from source to

destination as fast as possible until MaxCnt expires.

0: Stream3 not configured for mem to mem transfer

1: Stream3 configured for mem to mem transfer

When the stream 3 is configured as a memory-memory transfer, SoBurst relates to the source

side burst length, regardless of the value written in Dir bit (see below).

Bit 12 = Reserved. It must be always written to ‘0’.

Bit 13 = Dir: Direction transfer

This bit defines which field between DeSize and SoSize is used to compute burst and terminal

count word unit; since the side of DMA transfer requiring a burst is usually the peripheral one

this bit can be considered indicating the direction of the transfer, specifying if the peripheral is

acting as source or destination. The value written in this bit is ignored when the channel is

configured to perform a memory-to-memory transfer (Mem2Mem bit written to ‘1’).

0: SoSize defines the word unit for burst and terminal count (peripheral is the source).

1: DeSize defines the word unit for burst and terminal count (peripheral is the destination).

Bit 15:14 = Reserved. They must be always written to ‘0’.

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