STR720 datasheet(40/401 Pages) STMICROELECTRONICS

40 / 401 page

STR720 - ARCHITECTURE OVERVIEW

40/401

Figure 6. Reset General Timing

When a reset is asserted, RCCU registers will be preset in the following state:

■

Reference Clock (CLK clock), with no sub-division, will be used as System Clock and fed in

input to the PLL;

■

PLL will be switched off and bypassed with its multiplication factor preset to 1;

■

Most of peripheral clocks will be stopped (see Table 83: Peripheral clock and reset gating on

page 366)

It is up to the STR720 boot code to properly program the RCCU registers so as to use the

PLL, to set different division factors for APB_CLK, to enable or disable the peripheral clocks

according to application requirements.

5.8 Real Time Clock (RTC)

The real time clock is a 48 bits counter with a resolution of one period of the 32768 Hz input

clock. The counter is fed by the output clock of a 32768 Hz crystal oscillator. The RTC and the

oscillator are supplied by a dedicated 1.8 V stand-by power supply allowing the possibility to

switch off all the device keeping the counter running.

The counter is reset by a dedicated in pin which is supplied by 1.8 V too. The system reset

does not have any effect on the RTC.

RSTIN

external pin

CLK

AHB_CLK

...

768 cycles

8 cycles

CPU + PERIPH

Reset

CPU RUN

PERIPH. CK

≥ 50 ns

≤ 500 ns

RSTF

(after filter)

internal signal

STR720 数据表(PDF) 40 Page - STMicroelectronics

STR720 数据表(HTML) 40 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载