STR720 datasheet(102/401 Pages) STMICROELECTRONICS

102 / 401 page

STR720 - DRAM CONTROLLER (DRAMC)

102/401

Memory Address remapping

The AHB Interface remaps AHB address into DRAM row and column addresses; the 8, 9 and

10 bits wide column addresses are supported.

Table 27 shows how AHB address bits are mapped to MIA bits as row or column address.

Note that in the “Column” line bit 10 is always zero, while ba means: the same bit value used

in “Row” line. (This because bits [15:10] are never considered when used as column address).

The DRAM Controller reads the 27 less significant bits of the AHB address bus; they are

decomposed into:

■

Byte lanes MIBLSout[3:0], that are used to select which byte to read/write if the DRAM data

bus is larger than the data to read/write (for instance, when writing one byte into a DRAM

with a 32 bits data bus). They are decoded from HADDR[1:0] taking into account AHB data

width and DRAM data width.

■

Column address, as specified in Table 27, line “Column”. 8, 9 or 10 bits are really used by

the memory.

■

Row address, the remaining AHB address bits excluded the last two ones, HADDR[26:25].

■

Chip selects MICSout[3:0], to select one of four external bank to use. This is determined by

the value of HADDR[26:16] and the size of each external bank.

Table 27. DRAM Address bits versus AHB address bits

Memory

Data

Width

Address

Column

Address

Width

Memory Interface Address bits

15 14 13 12 11 10

8 bits

Column

9876543210

Row

2019181716151413121110

16 bits

Column

987654321

Row

32 bits

Column

98765432

Row

2019181716151413121110

2120191817161514131211

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