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数据搜索系统，热门电子元器件搜索 |
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STR720 数据表(PDF) 394 Page - STMicroelectronics |
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STR720 数据表(HTML) 394 Page - STMicroelectronics |
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394 / 401 page  STR720 - ELECTRICAL CHARACTERISTICS 394/401 1. See Figure 81 and Figure 82 for a definition of these parameters. 2. VDD(all) = 1.80 V ± 10%, VDD3(all) = 3.30 V ± 10%, TA = -40 / +85 °C unless otherwise specified. 3. Data based on design guidelines, not tested in production. 4. TC is CPU clock period expressed in ns. For example if CPU clock is set to run at 50 MHz, TC =20 ns. 5. Actual duration is configurable. See Chapter 11: EXTERNAL MEMORY INTERFACE (EMI) on page 115. Figure 81. EMI Read cycle timing (8-bit or 16-bit word) Figure 82. EMI Read cycle timing (32-bit word) ECSx EWEx EADD[21:0] EDATA[15:0] ERD (Input) Address Data Input wait cycle wait cycle wait cycle tRDS tRDH tRASR tRAH Note: this diagram shows the timing of 3 wait-state cycle read access. tRPR1 tSP tRASC tRPC1 wait cycle ECSx EWEx EADD[21:1] EDATA[15:0] ERD (Input) Address Data Input wait cycle tRDS tRDH tRASC tRAH tRPR2 tSP EADD[0] tSP Data Input tRDS tRDH tRPC1 Note: this diagram shows the timing of 1wait-state cycle read access. tRPC2 tRASR |
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