DRA821U4...ALM datasheet(127/252 Pages) TI

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Table 7-11. RESET_REQz Timing Requirements

see Figure 7-15

NO.

MIN

MAX UNIT

RST27 tw(RESET_REQzL) (1)

Pulse Width minimum, RESET_REQz active (low)

1200

(1)

Timing for RESET_REQz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.

Table 7-12. RESET_REQz initiates; RESETSTATz Switching Characteristics

see Figure 7-15

NO.

PARAMETER

MODE

MIN

MAX UNIT

RST28 td(RESET_REQzL-RESETSTATzL)

Delay time, RESET_REQz active (low)

to RESETSTATz active (low)

software control of

SOC_WARMRST_ISO_DONE

T(1)

CTRLMMR_WKUP_MAIN_WA

_RST_CTRL[0].SOC_

WARMRST_ISO_DONE_Z = 0

740

RST29 td(RESET_REQzH-RESETSTATzH)

Delay time, RESET_REQz inactive

(high) to RESETSTATz inactive (high)

2650*S

(2)

(1)

T = Reset Isolation Time (Software Dependent).

(2)

S = MCU_OSC0_XI/XO clock period.

RESET_REQz

RST28

RST27

RESETSTATz

RST29

Figure 7-15. RESET_REQz initiates; RESETSTATz Timing Requirements and Switching Characteristics

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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