DRA821U4...ALM datasheet(123/252 Pages) TI

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Table 7-6. PORz Timing Requirements

see Figure 7-11

NO.

MIN

MAX UNIT

RST4 th(MAIND_SUPPLIES_VALID - PORz)

Hold time, PORz active (low) at Power-up after all MAIN

DOMAIN supplies1 valid

1200

RST5 tw(PORzL)

Pulse Width minimum, PORz low after Power-up

1200

1. For definition of the MAIN DOMAIN supplies, see the Combined MCU and Main Domains Power-Up

sequence TBD.

PORz

RST4

RST5

MAIN DOMAIN

SUPPLIES VALID

Figure 7-11. PORz Timing Requirements

Table 7-7. MCU_PORz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics

see Figure 7-12

NO.

PARAMETER

MODE

MIN

MAX UNIT

RST10

td(MCU_PORzL-MCU_RESETSTATzL)

Delay time, MCU_PORz active (low) to

MCU_RESETSTATz active (low)

RST11

td(MCU_PORzH-MCU_RESETSTATzH)

Delay time, MCU_PORz inactive (high) to

MCU_RESETSTATz inactive (high)

POST

bypass

12000*S(1)

RST12

td(MCU_PORzL-RESETSTATzL)

Delay time, MCU_PORz active (low) to

RESETSTATz active (low)

RST13

td(MCU_PORzH-RESETSTATzH)

Delay time, MCU_PORz inactive (high) to

RESETSTATz inactive (high)

14500*S(1)

RST16

tw(MCU_RESETSTATzL)

Pulse Width Minimum MCU_RESETSTATz

low

3900*S(1)

RST17

tw(RESETSTATzL)

Pulse Width Minimum RESETSTATz low

2650*S(1)

(1)

S = MCU_OSC0_XI/XO clock period.

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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