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DRA821U4...ALM 数据表(PDF) 120 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 120 Page - Texas Instruments

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J7VCL_ELCH_06
T0
T1
T2
T3
T4
Valid Configuration
T0
T1
T2
T3
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU
(2)
(
0,
1,
2,
3,
VDDSHV
VDDSHV
VDDSHV
VDDSHV
4,
5 ,
6) ,
_3 3_
VDDSHV
VDDSHV
VDDSHV
VDDA
P
USB
(4)
(2)
(5)
(
_
_
0,
_
_
,
_
_
,
VDDA MCU PLLGRP
VDDA MCU TEMP VDDA ADC MCU
_
_
,
_
)
VDDA POR WKUP VDDA WKUP
(6)
VDD MCU
VDD MCU WAKE
VDDAR MCU
_
,
_
_
1,
_
(9)
VDD CORE VDD WAKE VDDA
P
SERDES
_
,
_
0
_0 8_
,
_0 8_
_ ,
_0 8_
VDDA
P
SERDES C VDDA
P
USB
VDDAR CORE VDDAR CPU
_
,
_
MCU_PORz
(10)(11)
PORz
(10)(11)
OSC1_XI, OSC1_XO
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
VDDS DDR BIAS VDDS DDR VDDS DDR C
_
_
,
_
,
_
_
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)
(3)
(
0,
1,
2,
3,
VDDSHV
VDDSHV
VDDSHV
VDDSHV
4,
54,
6) ,
_
0
VDDSHV
VDDSHV
VDDSHV
VDDS MMC
(3)
VDDA_OSC1, VDDA_PLLGRP8,
VDDA_PLLGRP6, VDDA_PLLGRP4,
VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1,
VDD_CPU
T4
(
_1 8_
,
_1 8_
)
VDDA
P
SERDES VDDA
P
USB
(7)
(
_0 8_
_
,
_0 8_
_
0)
VDDA
P
PLL DDR VDDA
P
DLL MMC
(9)
MCU_BOOTMODE[9:0], BOOTMODE[7:0]
(10)
Active
Active
Entry into MCU only
DDR Retention
Exit from MCU only
Note1
Note1
T
Δ1
Figure 7-8. Independent MCU and Main Domains, Entry and Exit of DDR Retention State
7.9.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
Entry into GPIO Retention state is accomplished by executing a power down sequence except for the 2 or 4
wake domains that remain energized. Exit from GPIO Retention state is accomplished by executing a power up
sequence with the 2 or 4 wake DDR domains remaining energized throughout the sequence.
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
120
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DRA821U-Q1



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