DRA821U4...ALM datasheet(118/252 Pages) TI

118 / 252 page

Markers showing approximate elapsed times that are dependent upon PDN feature set, component selection and power mapping.

Values shown are typical for PDNs combining MCU and Main voltage domains but could vary based upon PDN design.

Time Stamp definitions and (typical values for reference only):

T0 – MCU_PORz and PORz assert low to put all processor resources in safe state. (0 ms)

T1 – Main DDR, SRAM Core and SRAM CPU power domains start ramp-down. (0.5 ms)

T2 – All core voltages start supply ramp-down. (2.5 ms)

T3 – All 1.8V voltages start supply ramp-down. (3.0 ms)

T4 – All 3.3-V voltages start supply ramp-down. (3.5 ms)

Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.

Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.

VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8 V) power rail is required for compliant, high-speed

SD card operations. If SD card is not needed or standard data rates with fixed 3.3-V operation is acceptable, then domain can be

grouped with digital IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO

1.8-V power rail.

VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended

to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated,

then domain can be grouped with 3.3-V digital IO power rail either directly or through a supply filter.

VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply

for optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency

switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>

domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.

VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended

to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors

or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an

in-line supply filter is allowed.

VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance.

It is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively

impact jitter performance of PLL and DLL signals.

VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or

0.85-V RAM array (VDDAR_xxx) domains.

MCU_PORz and PORz must be asserted low for TΔ1 = 200 μs min to ensure SoC resources enter into safe state before any voltage

begins to ramp down.

Figure 7-6. Independent MCU and Main Domains, Primary Power- Down Sequencing

7.9.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing

Entry into MCU Only state is accomplished by executing a power down sequence except for the 4 MCU domains

that remain energized. Exit from MCU Only state is accomplished by executing a power up sequence with the

4 MCU domains remaining energized throughout the sequence. The example diagram shown is for an Isolated

MCU & Main PDN type with eMMC support.

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

118

Submit Document Feedback

Product Folder Links: DRA821U-Q1

DRA821U4...ALM 数据表(PDF) 118 Page - Texas Instruments

DRA821U4...ALM 数据表(HTML) 118 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载