DRA821U4...ALM datasheet(115/252 Pages) TI

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J7VCL_ELCH_03

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)

(C)

(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDA_3P3_USB

(E)

(C)

(F)

(VDDA_MCU_PLLGRP0,

VDDA_MCU_TEMP, VDDA_ADC_MCU,

VDDA_POR_WKUP, VDDA_WKUP)

(G)

VDD_MCU ,VDD_MCU_WAKE1, VDDAR_MCU

(J)

VDD_CORE, VDD_WAKE0, VDDA_0P8_SERDES,

VDDA_0P8_SERDES_C, VDDA_0P8_USB

VDDAR_CORE, VDDAR_CPU

MCU_PORz

(K)(L)

PORz

(K)(L)

OSC1_XI, OSC1_XO

(optional)

WKUP_LFOSC0_XI, WKUP_LFOSC0_XO

(optional)

WKUP_OSC0_XI, WKUP_OSC0_XO

VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C

MCU_BOOTMODE[9:0], BOOTMODE[7:0]

(K)

Valid Configuration

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)

(D)

(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5 , VDDSHV6)

VDDS_MMC0

(E)

(D),

VDDA_OSC1, VDDA_PLLGRP8,

VDDA_PLLGRP6, VDDA_PLLGRP4,

VDDA_PLLGRP0, VDDA_TEMP1, VDDA_TEMP0,

VDD_CPU

Note 1

(VDDA_1P8_SERDES, VDDA_1P8_USB)

(H)

Note 1

VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0

(I)

Terminology:

•

Primary = Essential power up sequence of all voltage domains to full active state.

•

VOPR MIN = Minimum operational voltage level that ensures functionality as specified in , Recommended Operating Conditions.

•

Ramp Up = Voltage supply transition time from off condition to VOPR MIN.

•

Domain_“n” = multiple instances of similar voltage domains (that is, dual voltage IO domains, VDDSHVn = VDDSHV0, VDDSHV1,

VDDSHV2 … VDDSHV6)

•

Domain_“xxx” = different signal type/protocol domains using same voltage supply type and level (that is, VDDA_1P8_xx =

VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)

Time stamp markers show approximate elapsed times that are dependent upon PDN feature set, component

selection and power mapping. Values shown are typical for PDNs supporting independent MCU and Main

voltage domains but could vary based upon PDN design.

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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