DRA821U4...ALM datasheet(117/252 Pages) TI

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7.9.2.5 Independent MCU and Main Domains Power- Down Sequencing

Figure 7-6 describes the device power-down sequencing.

J7VCL_ELCH_04

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)

(B)

(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDA_3P3_USB

(D)

(B)

(E)

(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP,

VDDA_ADC_MCU, VDDA_POR_WKUP, VDDA_WKUP)

(F)

VDD_MCU

(8)

VDD MCU WAKE

VDDAR MCU

VDDAR_CORE, VDDAR_CPU

MCU_PORz

(J)

PORz

(J)

OSC1_XI, OSC1_XO

(optional)

WKUP_LFOSC0_XI, WKUP_LFOSC0_XO

(optional)

WKUP_OSC0_XI, WKUP_OSC0_XO

VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)

(C)

(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5 , VDDSHV6)

VDDS_MMC0

(D)

(C),

VDDA_OSC1, VDDA_PLLGRP8,

VDDA_PLLGRP6, VDDA_PLLGRP4,

VDDA_PLLGRP0, VDDA_TEMP01, VDDA_TEMP0,

VDD_CPU

(VDDA_1P8_SERDES, VDDA_1P8_USB)

(G)

(VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0)

(H)

Δ1

MCU_BOOTMODE[9:0], BOOTMODE[7:0]

VDD_CORE, VDD_WAKE0, VDDA_0P8_SERDES,

VDDA_0P8_SERDES_C, VDDA_0P8_USB

Valid Configuration

Terminology:

•

Primary = Essential power down sequence of all voltage domains to complete off state.

•

VOPR MIN = Minimum operational voltage level that ensures functionality as specified in , Recommended Operating Conditions.

•

Ramp-down = voltage supply transition time from VOPR MIN to off condition.

•

Domain_“n” = multiple instances of similar voltage domains (that is, dual voltage IO domains, VDDSHVn = VDDSHV0, VDDSHV1,

VDDSHV2 … VDDSHV6)

•

Domain_“xxx” = different signal type/protocol domains using same voltage supply type and level (that is, VDDA_1P8_xx =

VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)

Time stamps:

www.ti.com

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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