DRA821U4...ALM datasheet(135/252 Pages) TI

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Table 7-21. WKUP_OSC0 Switching Characteristics – Crystal Mode

NAME

DESCRIPTION

MIN

TYP

MAX UNIT

CXI

XI Capacitance

1.55

CXO

XO Capacitance

1.35

CXIXO

XI to XO Mutual Capacitance

0.01

Start-up Time

9.5(1)

(1)

TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The

vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device

for optimum startup and operation over temperature/voltage extremes.

VDDA_WKUP

WKUP_OSC0_XO

Time

VSS

VDDA_WKUP (min.)

VDD_WKUP (min.)

VSS

VDD_WKUP

J7ES_WKUP_OSC_STARTUP_04

Figure 7-25. WKUP_OSC0 Start-up Time

7.9.4.1.1.1 Load Capacitance

The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined

by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors

CL1, CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to

WKUP_OSC0_XI and WKUP_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the

PCB designer should be able to extract parasitic capacitance for each signal trace. The WKUP_OSC0 circuits

and device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic

capacitance values are defined in Table 7-21.

J7ES_WKUP_OSC_CC_05

PCBXI

PCBXO

PCB

Signal Traces

Crystal Circuit

Components

WKUP_OSC0_XO

WKUP_OSC0_XI

Device

Figure 7-26. Load Capacitance

www.ti.com

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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