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HC705JB2GRS/H 数据表(PDF) 115 Page - NXP Semiconductors

部件名 HC705JB2GRS/H
功能描述  Industry standard M68HC05 CPU core
PDF  128 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JB2GRS/H 数据表(HTML) 115 Page - NXP Semiconductors

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August 28, 1998
GENERAL RELEASE SPECIFICATION
INSTRUCTION SET
REV 1.1
12-11
INC
opr
INCA
INCX
INC
opr,X
INC ,X
Increment Byte
M
← (M) + 1
A
← (A) + 1
X
← (X) + 1
M
← (M) + 1
M
← (M) + 1
—— ¤¤ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
ff
5
3
3
6
5
JMP
opr
JMP
opr
JMP
opr,X
JMP
opr,X
JMP ,X
Unconditional Jump
PC
← Jump Address
—————
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
JSR
opr
JSR
opr
JSR
opr,X
JSR
opr,X
JSR ,X
Jump to Subroutine
PC
← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP
← (SP) – 1
Push (PCH); SP
← (SP) – 1
PC
← Conditional Address
—————
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
5
6
7
6
5
LDA #
opr
LDA
opr
LDA
opr
LDA
opr,X
LDA
opr,X
LDA ,X
Load Accumulator
with Memory Byte
A
← (M)
— — ¤¤ —
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
LDX #
opr
LDX
opr
LDX
opr
LDX
opr,X
LDX
opr,X
LDX ,X
Load Index Register
with Memory Byte
X
← (M)
— — ¤¤ —
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
LSL
opr
LSLA
LSLX
LSL
opr,X
LSL ,X
Logical Shift Left
(Same as ASL)
—— ¤¤¤
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
3
6
5
LSR
opr
LSRA
LSRX
LSR
opr,X
LSR ,X
Logical Shift Right
— — 0
¤¤
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
ff
5
3
3
6
5
MUL
Unsigned Multiply
X : A
← (X) × (A)
0 — — — 0
INH
42
11
NEG
opr
NEGA
NEGX
NEG
opr,X
NEG ,X
Negate Byte
(Two’s Complement)
M
← –(M) = $00 – (M)
A
← –(A) = $00 – (A)
X
← –(X) = $00 – (X)
M
← –(M) = $00 – (M)
M
← –(M) = $00 – (M)
—— ¤¤¤
DIR
INH
INH
IX1
IX
30
40
50
60
70
ii
ff
5
3
3
6
5
NOP
No Operation
—————
INH
9D
2
Table 12-6. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
H I NZC
C
b0
b7
0
b0
b7
C
0
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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