DSP56362P datasheet(148/152 Pages) FREESCALE

148 / 152 page

DSP56362 Technical Data, Rev. 4

Index-2

Freescale Semiconductor

external clock operation 4

external interrupt timing (negative edge-triggered)

external level-sensitive fast interrupt timing 11

external memory access (DMA Source) timing 13

External Memory Expansion Port 14

functional groups 2

functional signal groups 1

General Purpose Input/Output 4

GPIO 4, 2, 19

GPIO timing 69

Ground 4

PLL 4

HDI08 4, 2, 10, 12, 13

DSP programming 6

DSP synchronization 6

Host synchronization 5

HDI08 timing 46

Host Interface 4, 2, 10, 12, 13

Host Interface timing 46

host port

configuration 9

Host Port considerations 5

Host programming 5

Host Request

Double 2

Single 2

instruction cache 3

internal clocks 4

interrupt and mode control 8

interrupt control 8

interrupt timing 7

external level-sensitive fast 11

external negative edge-triggered 11

synchronous from Wait state 12

Jitter 5

JTAG 20

JTAG Port 3

reset timing diagram 73

timing 70, 72

maximum ratings 1

Memory Expansion Port 3

mode control 8

Mode select timing 7

multiplexed bus 2

multiplexed bus timings

write 51

non-multiplexed bus 2

non-multiplexed bus timings

write 49

DSP56362P 数据表(PDF) 148 Page - Freescale Semiconductor, Inc

DSP56362P 数据表(HTML) 148 Page - Freescale Semiconductor, Inc

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