H8SX1663 datasheet(170/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 118 of 1102

REJ09B0294-0100

5.6.2

Interrupt Control Mode 2

In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the

interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels

in mask control. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.

1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

2. For multiple interrupt requests, the interrupt controller selects the interrupt request with the

highest priority according to the IPR setting, and holds other interrupt requests pending. If

multiple interrupt requests have the same priority, an interrupt request is selected according to

the default setting shown in table 5.2.

3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set

in EXR. When the interrupt request does not have priority over the mask level set, it is held

pending, and only an interrupt request with a priority over the interrupt mask level is accepted.

4. When the CPU accepts an interrupt request, it starts interrupt exception handling after

execution of the current instruction has been completed.

5. The PC, CCR, and EXR contents are saved to the stack area during interrupt exception

handling. The PC saved on the stack is the address of the first instruction to be executed after

returning from the interrupt handling routine.

6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority of the

accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7.

7. The CPU generates a vector address for the accepted interrupt and starts execution of the

interrupt handling routine at the address indicated by the contents of the vector address in the

vector table.

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