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H8SX1663 数据表(PDF) 174 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 174 Page - Renesas Technology Corp |
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174 / 1158 page  Section 5 Interrupt Controller Rev.1.00 Jun. 07, 2006 Page 122 of 1102 REJ09B0294-0100 Table 5.5 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus 16-Bit Bus Symbol On-Chip Memory 2-State Access 3-State Access 2-State Access 3-State Access Vector fetch S h 1 8 12 + 4m 4 6 + 2m Instruction fetch S I 1 4 6 + 2m 2 3 + m Stack manipulation S K 1 8 12 + 4m 4 6 + 2m [Legend] m: Number of wait cycles in an external device access. 5.6.5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to the CPU • Activation request to the DTC • Activation request to the DMAC • Combination of the above For details on interrupt requests that can be used to activate the DTC and DMAC, see table 5.2, section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller (DTC). Figure 5.6 shows a block diagram of the DTC, DMAC, and interrupt controller. |
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