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H8SX1663 数据表(PDF) 178 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 178 Page - Renesas Technology Corp |
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178 / 1158 page  Section 5 Interrupt Controller Rev.1.00 Jun. 07, 2006 Page 126 of 1102 REJ09B0294-0100 The priority level which is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1 and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU are reflected in bits CPUP2 to CPUP0. Table 5.7 shows the CPU priority control. Table 5.7 CPU Priority Control Control Status Interrupt Control Mode Interrupt Priority Interrupt Mask Bit IPSETE in CPUPCR CPUP2 to CPUP0 Updating of CPUP2 to CPUP0 0 Default I = any 0 B'111 to B'000 Enabled I = 0 1 B'000 Disabled I = 1 B'100 2 IPR setting I2 to I0 0 B'111 to B'000 Enabled 1 I2 to I0 Disabled |
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