H8SX1663 datasheet(181/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 129 of 1102

REJ09B0294-0100

5.8.2

Instructions that Disable Interrupts

Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and

XORC. After any of these instructions is executed, all interrupts including NMI are disabled and

the next instruction is always executed. When the I bit is set by one of these instructions, the new

value becomes valid two states after execution of the instruction ends.

5.8.3

Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.

The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has

updated the mask level with an LDC, ANDC, ORC, or XORC instruction, and for a period of

writing to the registers of the interrupt controller.

5.8.4

Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B and the EEPMOV.W instructions.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer

is not accepted until the transfer is completed.

With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt

exception handling starts at the end of the individual transfer cycle. The PC value saved on the

stack in this case is the address of the next instruction. Therefore, if an interrupt is generated

during execution of an EEPMOV.W instruction, the following coding should be used.

L1:

EEPMOV.W

MOV.W

R4,R4

BNE

5.8.5

Interrupts during Execution of MOVMD and MOVSD Instructions

With the MOVMD or MOVSD instruction, if an interrupt request is issued during the transfer,

interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved

on the stack in this case is the address of the MOVMD or MOVSD instruction. The transfer of the

remaining data is resumed after returning from the interrupt handling routine.

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