H8SX1663 datasheet(183/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 131 of 1102

REJ09B0294-0100

Section 6 Bus Controller (BSC)

This LSI has an on-chip bus controller (BSC) that manages the external address space divided into

eight areas.

The bus controller also has a bus arbitration function, and controls the operation of the internal bus

masters; CPU, DMAC, and DTC.

6.1

Features

• Manages external address space in area units

Manages the external address space divided into eight areas

Chip select signals (

CS0 to CS7) can be output for each area

Bus specifications can be set independently for each area

8-bit access or 16-bit access can be selected for each area

Burst ROM, byte control SRAM, or address/data multiplexed I/O interface can be set

An endian conversion function is provided to connect a device of little endian

• Basic bus interface

This interface can be connected to the SRAM and ROM

2-state access or 3-state access can be selected for each area

Program wait cycles can be inserted for each area

Wait cycles can be inserted by the

WAIT pin.

Extension cycles can be inserted while

CSn is asserted for each area (n = 0 to 7)

The negation timing of the read strobe signal (

RD) can be modified

• Byte control SRAM interface

Byte control SRAM interface can be set for areas 0 to 7

The SRAM that has a byte control pin can be directly connected

• Burst ROM interface

Burst ROM interface can be set for areas 0 and 1

Burst ROM interface parameters can be set independently for areas 0 and 1

• Address/data multiplexed I/O interface

Address/data multiplexed I/O interface can be set for areas 3 to 7

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