H8SX1663 datasheet(184/1158 Pages) RENESAS

184 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 132 of 1102

REJ09B0294-0100

• DRAM interface

DRAM interface is available as area 2

Row/column address-multiplexed output (8, 9, 10, or 11 bits)

Two

CAS signals control byte accesses for 16-bit data bus device

CAS assertion period can be extended by a program wait and a pin wait

Burst access can be performed in fast page mode

Tp cycle for ensuring a RAS precharge time can be inserted

CAS-before-RAS refresh (CBR refresh) and self refresh are selectable

• Synchronous DRAM interface

Synchronous DRAM interface is available as area 2

Row/column address-multiplexed output (8, 9, 10, or 11 bits)

DQM signals control byte access for 16-bit data bus device

Auto refresh and self refresh are selectable

CAS latency can be selected from 2 to 4

• Idle cycle insertion

Idle cycles can be inserted between external read accesses to different areas

Idle cycles can be inserted before the external write access after an external read access

Idle cycles can be inserted before the external read access after an external write access

Idle cycles can be inserted before the external access after a DMAC single address transfer

(write access)

• Write buffer function

External write cycles and internal accesses can be executed in parallel

Write accesses to the on-chip peripheral module and on-chip memory accesses can be executed

in parallel

DMAC single address transfers and internal accesses can be executed in parallel

• External bus release function

• Bus arbitration function

Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, DTC, and

external bus master

• Multi-clock function

The internal peripheral functions can be operated in synchronization with the peripheral

module clock (P

φ). Accesses to the external address space can be operated in synchronization

with the external bus clock (B

φ).

• The bus start (BS) and read/write (RD/WR) signals can be output.

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