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H8SX1663 数据表(PDF) 188 Page - Renesas Technology Corp

部件名 H8SX1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX1663 数据表(HTML) 188 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 136 of 1102
REJ09B0294-0100
6.2.2
Access State Control Register (ASTCR)
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space and enables/disables wait cycle insertion.
Bit
Bit Name
Initial Value
R/W
15
AST7
1
R/W
14
AST6
1
R/W
13
AST5
1
R/W
12
AST4
1
R/W
11
AST3
1
R/W
10
AST2
1
R/W
9
AST1
1
R/W
8
AST0
1
R/W
Bit
Bit Name
Initial Value
R/W
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
14
13
12
11
10
9
8
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 Access State Control
These bits select whether the corresponding area is to be
designated as 2-state access space or 3-state access
space. Wait cycle insertion is enabled or disabled at the
same time.
0: Area n is designated as 2-state access space
Wait cycle insertion in area n access is disabled
1: Area n is designated as 3-state access space
Wait cycle insertion in area n access is enabled
(n = 7 to 0)
7 to 0
All 0
R
Reserved
These are read-only bits and cannot be modified.



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