H8SX1663 datasheet(192/1158 Pages) RENESAS

192 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 140 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

W32

W31

W30

R/W

Area 3 Wait Control 2 to 0

These bits select the number of program wait cycles

when accessing area 3 while bit AST3 in ASTCR is 1.

000: Program wait cycle not inserted

001: 1 program wait cycle inserted

010: 2 program wait cycles inserted

011: 3 program wait cycles inserted

100: 4 program wait cycles inserted

101: 5 program wait cycles inserted

110: 6 program wait cycles inserted

111: 7 program wait cycles inserted



Reserved

This is a read-only bit and cannot be modified.

W22

W21

W20

R/W

Area 2 Wait Control 2 to 0

These bits select the number of program wait cycles

when accessing area 2 while bit AST2 in ASTCR is 1.

When SDRAM is connected, the CAS latency is

specified. At this time, W22 is ignored. The CAS latency

can be specified even if the wait cycle insertion is

disabled by ASTCR.

Selection of number of program wait cycles:

000: Program wait cycle not inserted

001: 1 program wait cycle inserted

010: 2 program wait cycles inserted

011: 3 program wait cycles inserted

100: 4 program wait cycles inserted

101: 5 program wait cycles inserted

110: 6 program wait cycles inserted

111: 7 program wait cycles inserted

Setting of CAS latency (W22 is ignored.):

00: Setting prohibited

01: SDRAM with a CAS latency of 2 is connected.

10: SDRAM with a CAS latency of 3 is connected.

11: SDRAM with a CAS latency of 4 is connected.

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