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H8SX1663 数据表(PDF) 196 Page - Renesas Technology Corp

部件名 H8SX1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX1663 数据表(HTML) 196 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 144 of 1102
REJ09B0294-0100
Bit
Bit Name
Initial
Value
R/W
Description
15
14
13
12
11
10
9
8
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS and Address Signal Assertion Period Control 1
These bits specify whether or not the Th cycle is to be
inserted (see figure 6.3). When an area for which bit
CSXHn is set to 1 is accessed, one Th cycle, in which
the
CSn and address signals are asserted, is inserted
before the normal access cycle.
0: In access to area n, the
CSn and address assertion
period (Th) is not extended
1: In access to area n, the
CSn and address assertion
period (Th) is extended
(n = 7 to 0)
7
6
5
4
3
2
1
0
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS and Address Signal Assertion Period Control 2
These bits specify whether or not the Tt cycle is to be
inserted (see figure 6.3). When an area for which bit
CSXTn is set to 1 is accessed, one Tt cycle, in which
the
CSn and address signals are retained, is inserted
after the normal access cycle.
0: In access to area n, the
CSn and address assertion
period (Tt) is not extended
1: In access to area n, the
CSn and address assertion
period (Tt) is extended
(n = 7 to 0)
Note:
*
In burst ROM interface, the CSXTn settings are ignored during CPU read accesses.



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