H8SX1663 datasheet(198/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 146 of 1102

REJ09B0294-0100

6.2.6

Idle Control Register (IDLCR)

IDLCR specifies the idle cycle insertion conditions and the number of idle cycles.

Bit

Bit Name

Initial Value

R/W

IDLS3

R/W

IDLS2

R/W

IDLS1

R/W

IDLS0

R/W

IDLCB1

R/W

IDLCB0

R/W

IDLCA1

R/W

IDLCA0

R/W

Bit

Bit Name

Initial Value

R/W

IDLSEL7

R/W

IDLSEL6

R/W

IDLSEL5

R/W

IDLSEL4

R/W

IDLSEL3

R/W

IDLSEL2

R/W

IDLSEL1

R/W

IDLSEL0

R/W

Bit

Bit Name

Initial

Value

R/W

Description

IDLS3

R/W

Idle Cycle Insertion 3

Inserts an idle cycle between the bus cycles when the

DMAC single address transfer (write cycle) is followed

by external access.

0: No idle cycle is inserted

1: An idle cycle is inserted

IDLS2

R/W

Idle Cycle Insertion 2

Inserts an idle cycle between the bus cycles when the

external write cycle is followed by external read cycle.

0: No idle cycle is inserted

1: An idle cycle is inserted

IDLS1

R/W

Idle Cycle Insertion 1

Inserts an idle cycle between the bus cycles when the

external read cycles of different areas continue.

0: No idle cycle is inserted

1: An idle cycle is inserted

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