H8SX1663 datasheet(195/1158 Pages) RENESAS

部件名	H8SX1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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195 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 143 of 1102

REJ09B0294-0100

Bus cycle

Data

RDNn = 0

RDNn = 1

(n = 7 to 0)

Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)

6.2.5

CS Assertion Period Control Registers (CSACR)

CSACR selects whether or not the assertion periods of the chip select signals (

CSn) and address

signals for the basic bus, byte-control SRAM, burst ROM, and address/data multiplexed I/O

interface are to be extended. Extending the assertion period of the

CSn and address signals allows

the setup time and hold time of read strobe (

RD) and write strobe (LHWR/LLWR) to be assured

and to make the write data setup time and hold time for the write strobe become flexible.

Bit

Bit Name

Initial Value

R/W

CSXH7

R/W

CSXH6

R/W

CSXH5

R/W

CSXH4

R/W

CSXH3

R/W

CSXH2

R/W

CSXH1

R/W

CSXH0

R/W

Bit

Bit Name

Initial Value

R/W

CSXT7

R/W

CSXT6

R/W

CSXT5

R/W

CSXT4

R/W

CSXT3

R/W

CSXT2

R/W

CSXT1

R/W

CSXT0

R/W

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