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H8SX1663 数据表(PDF) 200 Page - Renesas Technology Corp

部件名 H8SX1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX1663 数据表(HTML) 200 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 148 of 1102
REJ09B0294-0100
6.2.7
Bus Control Register 1 (BCR1)
BCR1 is used for selection of the external bus released state protocol, enabling/disabling of the
write data buffer function, and enabling/disabling of the
WAIT pin input.
Bit
Bit Name
Initial Value
R/W
15
BRLE
0
R/W
14
BREQOE
0
R/W
13
0
R
12
0
R
11
0
R/W
10
0
R/W
9
WDBE
0
R/W
8
WAITE
0
R/W
Bit
Bit Name
Initial Value
R/W
7
DKC
0
R/W
6
0
R/W
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
BRLE
0
R/W
External Bus Release Enable
Enables/disables external bus release.
0: External bus release disabled
BREQ, BACK, and BREQO pins can be used as I/O
ports
1: External bus release enabled*
For details, see section 9, I/O Ports.
14
BREQOE
0
R/W
BREQO Pin Enable
Controls outputting the bus request signal (
BREQO) to
the external bus master in the external bus released
state when an internal bus master performs an
external address space access.
0:
BREQO output disabled
BREQO pin can be used as I/O port
1:
BREQO output enabled



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