H8SX1663 datasheet(201/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 149 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

13, 12



All 0

Reserved

These are read-only bits and cannot be modified.

11, 10



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

WDBE

R/W

Write Data Buffer Enable

The write data buffer function can be used for an

external write cycle and a DMAC single address

transfer cycle.

The changed setting may not affect an external access

immediately after the change.

0: Write data buffer function not used

1: Write data buffer function used

WAITE

R/W

WAIT Pin Enable

Selects enabling/disabling of wait input by the

WAIT

pin.

0: Wait input by

WAIT pin disabled

WAIT pin can be used as I/O port

1: Wait input by

WAIT pin enabled

For details, see section 9, I/O Ports.

DKC

R/W

DACK Control

Selects the timing of DMAC transfer acknowledge

signal assertion.

DACK signal is asserted at the Bφ falling edge

DACK signal is asserted at the Bφ rising edge



R/W

Reserved

This bit is always read as 0. The write value should

always be 0.

5 to 0



All 0

Reserved

These are read-only bits and cannot be modified.

Note:

When external bus release is enabled or input by the

WAIT pin is enabled, make sure to set

the ICR bit to 1. For details, see section 9, I/O Ports.

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