H8SX1663 datasheet(177/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 125 of 1102

REJ09B0294-0100

5.7

CPU Priority Control Function Over DTC and DMAC

The interrupt controller has a function to control the priority among the DTC, DMAC, and the

CPU by assigning different priority levels to the DTC, DMAC, and CPU. Since the priority level

can automatically be assigned to the CPU on an interrupt occurrence, it is possible to execute the

CPU interrupt exception handling prior to the DTC or DMAC transfer.

The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level

of the DTC is assigned by bits DTCP2 to DTCP0 in CPUPCR. The priority level of the DMAC is

assigned by bits DMAP2 to DMAP0 in DMDR for each channel.

The priority control function over the DTC and DMAC is enabled by setting the CPUPCE bit in

CPUPCR to 1. When the CPUPCE bit is 1, the DTC and DMAC activation sources are controlled

according to the respective priority levels.

The DTC activation source is controlled according to the priority level of the CPU indicated by

bits CPUP2 to CPUP0 and the priority level of the DTC indicated by bits DTCP2 to DTCP0. If the

CPU has priority, the DTC activation source is held. The DTC is activated when the condition by

which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0

is greater than that of bits DTCP2 to DTCP0). The priority level of the DTC is assigned by the

DTCP2 to DTCP0 bits regardless of the activation source.

For the DMAC, the priority level can be specified for each channel. The DMAC activation source

is controlled according to the priority level of each DMAC channel indicated by bits DMAP2 to

DMAP0 and the priority level of the CPU. If the CPU has priority, the DMAC activation source is

held. The DMAC is activated when the condition by which the activation source is held is

cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to

DMAP0). If different priority levels are specified for channels, the channels of the higher priority

levels continue transfer and the activation sources for the channels of lower priority levels than

that of the CPU are held.

There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR.

Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt

mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function

to automatically assign the priority level. Therefore, the priority level is assigned directly by

software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the

CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0

bits in EXR).

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