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H8SX1663 数据表(PDF) 279 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 279 Page - Renesas Technology Corp |
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279 / 1158 page ![]() Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 227 of 1102 REJ09B0294-0100 6.9.10 DACK Signal Output Timing For DMAC single address transfers, the DACK signal assert timing can be modified by using the DKC bit in BCR1. Figure 6.37 shows the DACK signal output timing. Setting the DKC bit to 1 asserts the DACK signal a half cycle earlier. T ma1 T ma2 T 2 T 1 B φ DKC = 0 DKC = 1 Address bus D15 to D0 D15 to D0 Address cycle Data cycle CSn RD AH RD DACK BS RD/ WR Note: n = 3 to 7 Address Read data RDNn = 0 RDNn = 1 Address Read data Figure 6.37 DACK Signal Output Timing |
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