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H8SX1663 数据表(PDF) 283 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 283 Page - Renesas Technology Corp |
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283 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 231 of 1102 REJ09B0294-0100 6.10.6 Controlling Column Address Output Cycle The number of column address output cycles can be changed from two to three clock cycles by setting the CAST bit in DRAMCR. Set the bit according to the DRAM to be used and the frequency of this LSI so that the CAS pulse width can be optimal. Figure 6.39 shows a timing example when the number of column address output cycles is set to three clock cycles. T p T r T c1 T c2 T c3 Address bus Row address Column address B φ RAS LUCAS LLCAS WE OE (RD) WE OE (RD) Data bus High High Read Write Data bus BS RD/ WR Figure 6.39 Access Timing Example of Column Address Output Cycles for 3 Clock Cycles (RAST = 0) |
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