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H8SX1663 数据表(PDF) 280 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 280 Page - Renesas Technology Corp |
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280 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 228 of 1102 REJ09B0294-0100 6.10 DRAM Interface In this LSI, area 2 in the external space can be used as the DRAM interface space. Up to 8 Mbytes of DRAM is directly connected via the DRAM interface. 6.10.1 Setting DRAM Space Area 2 can be specified as the DRAM space by the DRAME and DTYPE bits in DRAMCR. Table 6.20 lists the relationship among the DRAME and DTYPE bits and area 2 interfaces. The bus settings of the DRAM space such as bus width and wait cycle number depend on area 2 settings. Table 6.20 Relationship Among DRAME and DTYPE and Area 2 Interfaces DRAME DTYPE Area 2 Interface 0 × Basic bus space (initial state)/byte-control SRAM space 1 0 DRAM space 1 1 SDRAM space [Legend] ×: Don't care 6.10.2 Address Multiplexing A Row address and a column address are multiplexed in the DRAM space. Select the number of row address bits to be shifted with bits MXC1 and MXC0 in DRAMCR. Table 6.21 lists the relationship among bits MXC1 and MXC0 and shifted bit number. Table 6.21 Relationship Among MXC1 and MXC0 and Shifted Bit Count DRAMCR MXC1 1 1 0 0 0 1 1 0 8 bits 9 bits 10 bits 11 bits 8/16 bits 8/16 bits 8/16 bits 8/16 bits MXC0 A27 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 A17 - A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 A17 -- A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 A17 --- A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 A17 ---- A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row address Column address Row address Column address Row address Column address Row address Column address Shit Bit Count Data Bus Width Address External Address Pin |
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