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H8SX1663 数据表(PDF) 281 Page - Renesas Technology Corp

部件名 H8SX1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX1663 数据表(HTML) 281 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 229 of 1102
REJ09B0294-0100
6.10.3
Data Bus
The data bus width of the DRAM space can be selected from 8 and 16 bits by bits ABWH2 and
ABWL2 in ABWCR. DRAM with 16-bit words can be connected directly to 16-bit bus width
space.
D7 to D0 are valid in 8-bit DRAM space, and D15 to D0 are valid in 16-bit DRAM space.
The data endian format can be selected by bit LE2 in ENDIANCR. For details on the access size
and alignment, see section 6.5.6, Endian and Data Alignment.
6.10.4
I/O Pins Used for DRAM Interface
Table 6.22 shows the pins used for the DRAM interface.
Table 6.22
I/O Pins for DRAM Interface
Pin
DRAM
Selected
Name
I/O
Function
WE
WE
Write enable
Output
Write enable signal for accessing the
DRAM interface
RAS
RAS
Row address
strobe
Output
Row address strobe when the DRAM
space is specified as area 2
LUCAS/
DQMLU
LUCAS
Lower-upper
column address
strobe
Output
• Lower-upper column address strobe
when the 32-bit DRAM space is
accessed
• Upper column address strobe when the
16-bit DRAM space is accessed
LLCAS/
DQMLL
LLCAS
Lower-lower
column address
strobe
Output
• Lower-lower column address strobe
when the 32-bit DRAM space is
accessed
• Lower column address strobe when the
16-bit DRAM space is accessed
OE
OE
Output enable
Output
Output enable signal when the DRAM
space is accessed
WAIT
WAIT
Wait
Input
Wait request signal used when an external
address space is accessed
A17 to A0
A17 to A0
Address pin
Output
Multiplexed address/data output pin
D15 to D0
D15 to D0
Data pin
Input/
output
Data input/output pin



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