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H8SX1663 数据表(PDF) 307 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 307 Page - Renesas Technology Corp |
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307 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 255 of 1102 REJ09B0294-0100 6.11.2 Address Multiplexing A Row address and a column address are multiplexed in the SDRAM space. Select the number of row address bits to be shifted with bits MXC1 and MXC0 in DRAMCR. The precharge set command (Precharge-sel) is output on the upper column address. Table 6.25 lists the relationship among bits MXC1 and MXC0 and shifted bit number. Table 6.25 Relationship Among MXC1 and MXC0 and Shifted Bit Count DRAMCR Row address Column address Row address Column address MXC1 0 0 8 bits 8 bits 16 bits MXC0 A23 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A18 -- A23 A22 A21 A20 A19 P/A18* A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A23 to A18 -- A23 A22 A21 A20 A19 P A9A8A7A6A5A4A3A2A1A0 A23 to A18 -- A23 A22 A21 A20 P/A19* A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A23 to A18 -- A23 A22 A21 A20 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row address Column address Row address Column address 1 0 10 bits 8 bits 16 bits A23 to A18 -- -- A23 A22 A21 P/A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 to A18 -- -- A23 A22 A21 P A9A8A7A6A5A4A3A2A1A0 A23 to A18 -- -- A23 A22 P/A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A23 to A18 -- -- A23 A22 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row address Column address Row address Column address 0 1 9 bits 8 bits 16 bits A23 to A18 A17 -- A23 A22 A21 A20 P/A19* A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A18 A17 -- A23 A22 A21 A20 P A9A8A7A6A5A4A3A2A1A0 A23 to A18 A17 -- A23 A22 A21 P/A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A18 A17 -- A23 A22 A21 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row address Column address Row address Column address 1 1 11 bits 8 bits 16 bits A23 to A18 A17 - --- A23 A22 P/A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A23 to A18 A17 - --- A23 A10 P A9A8A7A6A5A4A3A2A1A0 A23 to A18 A17 - --- A23 P/A22* A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A23 to A18 A17 - --- A11 P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Note: * When issuing the PALL command, precharge-sel = 1 is output and when issuing the ACTIV command, a corresponding address is output. Shift Bit Count Data Bus Width Address External Address Pin 6.11.3 Data Bus Either 8 or 16 bits can be selected as the data bus width of the SDRAM space by bits ABWH2 and ABWL2 in ABWCR. SDRAM with 16-bit words can be connected directly to 16-bit bus width space. D7 to D0 are valid in 8-bit SDRAM space and D15 to D0 are valid in 16-bit SDRAM space. The data endian format can be selected by bit LE2 in ENDIANCR. For details on the access size and alignment, see section 6.5.6, Endian and Data Alignment. |
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