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H8SX1663 数据表(PDF) 308 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 308 Page - Renesas Technology Corp |
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308 / 1158 page ![]() Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 256 of 1102 REJ09B0294-0100 6.11.4 I/O Pins Used for DRAM Interface Table 6.26 shows the pins used for the SDRAM interface. Since a CS pin functions as an input after a reset, set the bit in PFCR to 1 to output the CS signal. For details, see section 9, I/O Ports. To enable the SDRAM interface, select the appropriate MCU operating mode. For details, see section 3, MCU Operating Modes. Table 6.26 I/O Pins for SDRAM Interface Pin DRAM Selected Name I/O Function RAS RAS Row address strobe Output Row address strobe when the SDRAM space is specified as area 2 CAS CAS Column address strobe Output Column address strobe when the SDRAM space is specified as area 2 WE WE Write enable Output Write enable signal for accessing the SDRAM interface OE/CKE CKE Clock enable Output Clock enable signal when the SDRAM space is specified as area 2. LLCAS/ DQMLU DQMLU Lower-upper data mask enable Output Upper data mask enable when the 16- bit SDRAM space is accessed LLCAS/ DQMLL DQMLL Lower-lower data mask enable Output • Lower data mask enable when the 16-bit SDRAM space is accessed • Data mask enable when the 8-bit SDRAM is accessed A17 to A0 A17 to A0 Address pin Output Multiplexed row/column-address output pin D15 to D0 D15 to D0 Data pin Input/ output Data input/output pin (PA7) PB7 SD φ Clock Output SDRAM clock CS2 CS Chip select Output Strobe signal indicating that SDRAM is selected |
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