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H8SX1663 数据表(PDF) 309 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 309 Page - Renesas Technology Corp |
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309 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 257 of 1102 REJ09B0294-0100 6.11.5 Basic Timing Figures 6.60 and 6.61 show a basic access timing of the SDRAM space. A basic read cycle consists of five clock cycles: one precharge cycle (Tp), one row address output cycle (Tr), and three column address output cycles (Tc1, Tcl, and Tc2). A basic write cycle consists of four clock cycles: one precharge cycle (Tp), one row address output cycle (Tr), and two column address output cycles (Tc1 and Tc2). When the SDRAM space is selected, the WAITE bit in BCR, the RAST and CAST bits in DRAMCR, bits RCW1 and RCW0 in REFCR are ignored. Tp Tr Tc1 Tcl Tc2 Address bus Row address Column address SD φ CS Precharge-sel RAS CAS WE CKE PALL ACTV READ NOP DQMLU DQMLL D7 to D0 BS RD/ WR D15 to D8 Row address Figure 6.60 SDRAM Basic Read Access Timing (CAS Latency = 2) |
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